Heterointegration of materials using deposition and bonding

ABSTRACT

A semiconductor structure including a first substrate, and an epitaxial layer bonded to the substrate. The epitaxial layer has a threading dislocation density of less than 10 7 cm −2  and an in-plane lattice constant that is different from that of the first substrate and a second substrate on which the epitaxial layer is fabricated. In another embodiment, there is provided a method of processing a semiconductor structure including providing a first substrate; providing a layered structure including a second substrate having an epitaxial layer provided thereon, the epitaxial layer having an in-plane lattice constant that is different from that of the first substrate and a threading dislocation density of less than 10 7  cm −2 ; bonding the first substrate to the layered structure; and removing the second substrate.

PRIORITY INFORMATION

[0001] This application claims priority from provisional applicationSer. No. 60/177,084 filed Jan. 20, 2000.

BACKGROUND OF THE INVENTION

[0002] The invention relates to the field of heterointegration ofmaterials using deposition and bonding.

[0003] The goal of combining different materials on a common substrateis desirable for a variety of integrated systems. Specifically, it hasbeen a long-standing desire to combine different semiconductor and oxidematerials on a common useful substrate such as a silicon substrate.However, just as the different materials properties are beneficial fromthe system application perspective, other properties make such materialscombinations problematic in processing.

[0004] For example, semiconductor materials with different propertiesoften have different lattice constants. Therefore, deposition of onesemiconductor material on top of another substrate material results inmany defects in the semiconductor layer, rendering it useless forpractical application. Another method of integrating materials isthrough the use of wafer bonding. The bonding process removes thelattice mismatch problem. However, this problem is replaced with amismatch in thermal expansion. Due to the different thermal expansioncoefficients in the bonded materials, the materials cannot besubsequently processed or annealed at optimum temperatures withoutinducing material degradation (i.e. greater residual stress orintroduction of dislocations). A final issue is that due to thedifferent material properties, the bulk crystal materials are oftendifferent size (boule diameter). This disparity is undesirable for waferbonding since only a portion of the composite is useful fordevice/system fabrication.

SUMMARY OF THE INVENTION

[0005] Accordingly, the invention provides a semiconductor structureincluding a first substrate, and an epitaxial layer bonded to thesubstrate. The epitaxial layer has a threading dislocation density ofless than 10⁷ cm⁻² and an in-plane lattice constant that is differentfrom that of the first substrate and a second substrate on which theepitaxial layer is fabricated. In an exemplary embodiment, the epitaxiallayer is a segment of a previously fabricated layered structureincluding the second substrate with a compositionally graded layer andthe epitaxial layer provided thereon. The second substrate and thegraded layer are removed subsequent to the layered structure beingbonded to the first substrate.

[0006] In accordance with another exemplary embodiment of the invention,there is provided a method of processing a semiconductor structureincluding providing a first substrate; providing a layered structureincluding a second substrate having an epitaxial layer provided thereon,the epitaxial layer having an in-plane lattice constant that isdifferent from that of the first substrate and a threading dislocationdensity of less than 10⁷ cm⁻²; bonding the first substrate to thelayered structure; and removing the second substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007]FIG. 1 is a graph showing the strain induced when a 500 μm thickGaAs wafer and a 500 μm thick Si wafer are bonded at room temperatureand annealed at high temperature, and bonded at high temperature andcooled to room temperature;

[0008]FIG. 2 is a graph showing the curvature induced when a 500 μmthick GaAs wafer and a 500 μm thick Si wafer are bonded under twoconditions: bonding at room temperature and subsequently annealing athigh temperature anneal, and bonding at high temperature andsubsequently cooling to room temperature;

[0009] FIGS. 3A-3D are a process flow block diagram for producing a highquality SiGe layer on Si without the presence of a graded buffer layerusing wafer bonding and substrate removal;

[0010] FIGS. 4A-4D are a process flow block diagram showingplanarization steps used to improve the surface quality before bondingor after substrate removal;

[0011]FIG. 5A-5F are a process flow block diagram for producing a highquality InGaAs layer directly on Si by iterating the graded layerbonding process;

[0012]FIG. 6 is a cross-sectional transmission electron micrograph of arelaxed, low dislocation density SiGe film on an oxidized substrate; and

[0013] FIGS. 7A-7D are a process flow block diagram for producing highquality mismatched epitaxial layers directly on Si using patternedtrenches in the epitaxial layer as a sink for dislocations and forstrain relief.

DETAILED DESCRIPTION OF THE INVENTION

[0014] The invention involves a semiconductor structure and a method ofproducing a thin, low dislocation density, epitaxial film directly on alattice mismatched substrate. A thin layer of a material can bedeposited on a substrate including a different material using a gradedlayer to taper any materials properties difference. The gradedcomposition layer often poses a limit to many applications, since thegraded layer possesses many dislocations and is quite thick relative toother epitaxial layers and to typical step-heights in CMOS processes.However, if the surface of the deposited semiconductor material isrelatively free of defects, the surface can be bonded to anothersubstrate. Subsequently, the original substrate and graded layer can beremoved to produce an integrated layer on the desired substrate withoutthe graded region.

[0015] Three semiconductor substrates dominate the substrate market: Si,GaAs, and InP. The volumes and diameters of the wafers scaleaccordingly: Si has the largest wafer size (8 inch, moving to 12 inch)and volumes, GaAs is the next largest (4 inch, moving to 6 inchdiameter), and InP trails with the smallest volumes and wafer size (2inch, moving to 3 and 4 inch). The lattice constant of the substrateincreases from Si to GaAs to InP, and the mechanical strength decreaseswith increasing lattice constant. Thus, Si is the easiest crystal togrow to large diameter with great perfection, whereas InP is the mostdifficult of the three.

[0016] Although the mechanical strength was one of the many reasons thatSi began as the favored substrate, the ability to makemetal-oxide-semiconductor field-effect-transistors (MOSFETs) allowedmarkets, chip size, and wafer size to grow rapidly, installing aninfrastructure world-wide that continues to make Si the low-costplatform for microelectronics. GaAs and InP are useful in someelectronics applications; however, their markets are primarily driven byoptoelectronics. Integrating GaAs or InP devices on a Si substrate hastremendous advantages since it allows for the integration of Sielectronics with optical devices. However, due to the discrepancy inwafer diameters, a straight bonding process results in only a portion ofthe Si wafer being covered with GaAs or InP. Because the wafer sizedifference involves both market size and technology issues, it is asignificant barrier to the successful integration of III-V materialswith Si using wafer bonding.

[0017] The other issue in question is the thermal expansion differencebetween the substrate materials being bonded. FIG. 1 is a plot of thestrain developed if a GaAs wafer and a Si wafer (each 500 μm thick) arebrought in contact at room temperature and heated for bonding, as wellas the case where the wafers are bonded at high temperature and cooleddown to room temperature. The strains are approximate, using only thelinear term in the thermal expansion of the lattice with temperature.Note that if the wafers are bonded at room temperature and heated, asignificant strain develops in the bonded pair. This strain can eithercrack the assembly, or simply cause the wafers to debond. The additionaldriving force for debonding can be calculated using the Stoney formula,which describes the curvature of a composite structure like the twobonded wafers:${( \frac{d_{f} + d_{s}}{2} )F_{f}} = {\frac{w}{12R}\lbrack {{Y_{f}d_{f}^{3}} + {Y_{s}d_{s}^{3}}} \rbrack}$

[0018] where d_(s) is the thickness of the substrate, d_(f) is thethickness of the film, F_(f) is the force on the film, w is the width ofthe film and substrate, R is the radius of curvature, Y_(f) is thebiaxial modulus of the film, and Y_(s) is the biaxial modulus of thesubstrate.

[0019] If the substrate and film have an equal thickness of 500 μm(d=d_(s)=d_(f)), the formula simplifies to:$R = {{\frac{d}{12\quad ɛ}\lbrack {1 + \frac{Y_{Si}}{Y_{GaAs}}} \rbrack}.}$

[0020]FIG. 2 is a plot of the curvature of the substrate composite of aGaAs wafer bonded to a Si wafer, for the case of bonding at roomtemperature and heating, as well as bonding at high temperature andcooling. In the case of bonding at room temperature and heating, thecombination of the strain shown in FIG. 1 and the resulting curvatureshown in FIG. 2 leads to debonding. In the case of bonding at hightemperature, the bonding is very strong, and therefore the substratecomposite at room temperature is curved, rendering the material uselessin most fabrication facilities, especially Si CMOS facilities, wherewafer flatness is very important for compatibility with processingequipment. In addition, the substrate composite contains enough strainenergy that it is energetically feasible to introduce cracks, and thusthe composite tends to fracture spontaneously or with slight mechanicalabrasion.

[0021] In order to understand how the current invention circumvents thetwo issues described, the case of integrating a Ge layer or GaAs layeronto a crystalline Si substrate will now be described. FIGS. 3A-3D are aprocess flow block diagram for producing a high quality SiGe layer on Siwithout the presence of a graded buffer layer using wafer bonding andsubstrate removal in accordance with an exemplary embodiment of theinvention.

[0022] Initially, a graded layer 302 of SiGe is provided on a Sisubstrate 300 to produce the desired lattice constant with a minimalnumber of threading dislocations at the top surface. For a review ofthis process, see E. A. Fitzgerald et al., J. Vac. Sci. and Tech. B 10,1807 (1992), incorporated herein by reference. Through this process, auniform SiGe layer 304 is produced at the surface of the structure, eventhough a silicon substrate exists below. The Ge concentration in thisSi_(1-x)Ge _(x) virtual substrate can range from 0.5-100% (0.005 <x<1).The SiGe surface is then bonded to a second silicon wafer 306, or, ifthe graded layer is graded to pure Ge, a Ge or GaAs layer deposited onthe Ge can be bonded to the silicon wafer. Whatever the surface layercomposition, the original substrate 300 (on which the graded layer wasdeposited) as well as the graded layer 302 are then removed, producing arelaxed novel material directly on silicon.

[0023] Although compositional grading allows control of the surfacematerial quality, strain fields due to misfit dislocations in the gradedlayer can lead to roughness at the surface of the epitaxial layer. Thisroughness poses a problem for wafer bonding, where smooth surfaces arerequired for strong, uniform bonded interfaces. Implementation of aplanarization technique, such as chemomechanical polishing (CMP), beforebonding will eliminate this surface roughness and thus enable highquality bonds.

[0024] FIGS. 4A-4D are a process flow block diagram showingplanarization steps used to improve the surface quality before bondingor after substrate removal. Initially, a graded layer 402 is provided ona substrate 400 to produce the desired lattice constant with a minimalnumber of threading dislocations at the top surface. A uniform epitaxiallayer 404 for transfer is produced at the surface of the structure. Thesurface of the epitaxial layer 404 is then planarized so it can bebonded to a second substrate 406. The original substrate 400 (on whichthe graded layer was deposited) as well as the graded layer 402 are thenremoved, resulting in a relaxed material directly on the secondsubstrate.

[0025] Additionally, planarization techniques can be used on the relaxedlayer after the original substrate and graded layer are removed. Thisstep is useful if the substrate removal produces a rough surface (as indelamination techniques).

[0026] The practical success of the invention is that the thermalexpansion coefficient of the two substrate materials are similar oridentical, and the wafers are of the same diameter. Thus, the gradedlayer method of creating a virtual substrate material on top of siliconremoves the two constraints that have prevented wafer bonding fromeffectively producing large areas of heterogeneously integratedmaterials. With this technique, GaAs, Ge, and any concentration of SiGecan be integrated on Si without the presence of thick graded layers.

[0027] It is important to note that although the wafer composite isguaranteed to be nearly flat due to the two substrates being identicalmaterial, the epitaxial layers have different thermal expansioncoefficients than the substrates and thus experience a large stress andstrain. If the thermally induced strain is high enough, it is possibleto cause further relaxation of the epitaxial layers. In principle, thisrelaxation can be benign. For example, if the strain level is greatenough to command threading dislocation motion at a given temperature,but the strain level is low enough that the nucleation of newdislocations is not encouraged, then no negative effect will beencountered.

[0028] This level of strain can be beneficial. If patterns have beenetched in the epitaxial layers before bonding, the threading dislocationmotion created by the strain moves the threading dislocations to thepattern edges, thus lowering the effective threading dislocation densityat the top surface of the epitaxial layers. However, too high a strainlevel due to excessive heating of the bonded composite will nucleate newdislocations, increasing the threading dislocation density in theepitaxial layer. A guideline for defining the excess strain level fordislocation nucleation can be gleaned from the known experimental datain a myriad of lattice-mismatched semiconductor systems. For latticemismatches near 1% or less, the threading dislocation density is usuallyless than 10⁷ cm⁻², and thus may not increase the threading dislocationdensity over the level already present in the layers (10⁵−10⁶ cm⁻²). Forgreater than approximately 1-1.5% strain, the threading dislocationdensity in relaxed material is quite high. Thus, the objective is to notlet the strain in the sandwiched epitaxial layer approach 1% in order tominimize the chance for increased threading dislocation density.

[0029] The synergy of combining the graded layer and bonding methodsextends beyond the embodiments described. For example, the process canbe repeated multiple times, and the process remains economical sinceinexpensive Si wafers are used for the original host wafers. FIGS. 5A-5Fare a process flow block diagram for producing a high quality InGaAslayer directly on Si by iterating the graded layer bonding process.Multiple process iterations can be used to integrate InGaAs alloys onSi. In order to produce InGaAs on Si with only compositional grading, aSi substrate 500 is graded from Si to a pure Ge layer 504 using a SiGegrading layer 502, and subsequently graded from GaAs to InGaAs bydepositing a GaAs layer 506 and grading the In composition with a gradedlayer 510. However, for high In concentrations, a thick region of gradedInGaAs is needed to keep the threading dislocation density low at thesurface. This great thickness results in cracking upon cooling from thegrowth temperature.

[0030] The invention can be used to first create a thin layer of GaAs506 on a Si substrate 508 in which the Ge 504 and SiGe 502 graded layershave been removed. Subsequently, In can be compositionally graded toachieve the desired InGaAs layer 512. The fact that the SiGe and Ge areremoved allows for the grading of thicker InGaAs layers, since Ge has asimilar thermal expansion coefficient as the III-V materials. If thegraded InGaAs layer were undesirable in a particular application, thenthe process can be repeated to produce InGaAs directly on a Si substrate514. If the In concentration in the graded layer 510 is graded to near50% In, then this method can be used for creating InP layers on Si,useful for optoelectronic integration of λ=1.55 μm devices with Sielectronics.

[0031] It will be appreciated that a thin Ge or III-V material layer onSi can be created with the process shown in FIGS. 5A-5F. These materialsare very useful in fabricating optoelectronic integrated circuits(OEICs) on Si. The thin layer might be Ge or GaAs or In_(0.5)Ga_(0.5)Pafter SiGe grading, or may also be InGaAs or InP after InGaAs grading.Essentially, by utilizing either one or multiple bonding sequences, thinlayers of Si_(1-t)Ge_(t),Al_(v)(In_(w)Ga_(1-w))_(1-v)(As_(1-y)P_(y))_(1-z) can be produced on amismatched substrate where 0.005<t<1, 0<v<1, 0<w<1, 0<x<1, 0<y<1, and0<z<1. These thin layers are removed from the areas where Si electronicsare to be fabricated using standard photolithography. The remainingareas containing the thin material for optoelectronics are protectedwith a SiO₂ layer or other material during Si circuit processing. Aftersubstantial Si circuit processing, removing the SiO₂ exposes the thinoptoelectronic areas, and subsequently optoelectronic devices arefabricated.

[0032] An advantageous feature of the invention is the ability tointegrate a thin layer. After removal of the original wafer and gradedlayer, only a thin layer of the thermally mismatched material ispresent. Thus, the thin film on thick substrate approximation holds:$R = {{\frac{d}{12\quad ɛ}\lbrack {1 + \frac{Y_{Si}}{Y_{GaAs}}} \rbrack}.}$

[0033] For a thin film of 0.1 μm GaAs on a 500 μm Si substrate, theradius of curvature is always much greater than 10⁴ cm for thetemperature range of room T to 750C. for the structure. Such a smallamount of curvature will not affect most processing. However, if thereis a need to remove this small curvature, other epitaxial layers and/orlayers on the backside of the wafer can be deposited to easilycompensate for the strain, leading to wafers with less curvature.

[0034] All of the provided examples exemplifysemiconductor/semiconductor bonding. However, other materials present onthe wafer surface can be present as well and included by bonding intothe structure. For example, instead of bonding only to bare Si surfaces,the epitaxial wafer can be bonded to a Si wafer coated with SiO₂. Usingthe process described, a thin GaAs/SiO₂/Si structure is created, whichis very useful for optical interconnects. The SiO₂ layer allows for bothoptical and electronic isolation of the top optoelectronic layer. Anexample of bonding a relaxed SiGe alloy on Si to SiO₂/Si is shown inFIG. 6. FIG. 6 is a cross-section transmission electron micrograph of anexemplary SiGe/SiO₂/Si structure. The process used to create thematerial is the same as shown in FIGS. 3A-3D, except the SiGe has beenbonded to a Si wafer with SiO₂ on its surface.

[0035] In addition, in an alternative exemplary embodiment of theinvention, a structure can be fabricated in accordance with thepreviously described process in which the epitaxial layer is eventuallyapplied to a glass substrate rather than a Si substrate. The glasssubstrate would need to have a thermal expansion coefficient that issimilar to that of the substrate on which the epitaxial layer isdeposited, e.g., Si.

[0036] FIGS. 7A-7D are a process flow block diagram for producing highquality mismatched epitaxial layers directly on Si using patternedtrenches in the epitaxial layer as a sink for dislocations and forstrain relief in accordance with an alternative exemplary embodiment ofthe invention. A graded layer 702, e.g., SiGe, Ge or GaAs, is providedon a first Si substrate 700. This layer is graded until a uniform layer704 is produced. The uniform layer 704 is then patterned with viasand/or trenches before the bonding process. A second Si substrate isbonded to the uniform layer 704. Subsequently, the first Si substrate700 and the graded layer 702 are removed resulting in a uniform layer,e.g., Si_(1-y)Ge_(y), provided directly on a Si substrate.

[0037] In this way, tensile stress in the original graded structure isrelieved, aiding the bonding operation. This variant also produces aflat structure with isolated patterns after release. For example, anarray of trenches produces a series of mesas on the surface, and afterbonding and removal, these mesas are areas of isolated, relaxed layers.In this embodiment, the epitaxial layer will not contribute to thermalbowing of the new structure. Additionally, since these mesas areisolated, the edges of the mesas act as sinks for dislocations, and thusthermal cycling of the material further reduces the threadingdislocation density.

[0038] In all of the above processes, there are various ways of removingthe graded layer/original substrate. One method is the well-knownetch-back process, where the substrate is physically ground until quitethin, and then a chemical etch is used to stop at a particular layer.Another technique is the hydrogen-implant technique, in which a highdose of hydrogen is implanted below the surface of the layer to bereleased (in this case, the surface of the original substrate plusgraded layer and uniform layer). After bonding, it is possible tofracture the implanted region, removing the original graded layer andsubstrate, and leaving the desired transferred layer.

[0039] Although the present invention has been shown and described withrespect to several preferred embodiments thereof, various changes,omissions and additions to the form and detail thereof, may be madetherein, without departing from the spirit and scope of the invention.

What is claimed is:
 1. A semiconductor structure comprising: a firstsubstrate; and an epitaxial layer bonded to said substrate, saidepitaxial layer having a threading dislocation density of less than 10⁷cm⁻² and an in-plane lattice constant that is different from that ofsaid first substrate and a second substrate on which said epitaxiallayer is fabricated.
 2. The structure of claim 1, wherein said epitaxiallayer is a segment of a previously fabricated layered structureincluding said second substrate with a compositionally graded layer andsaid epitaxial layer provided thereon, said second substrate and saidgraded layer being removed subsequent to said layered structure beingbonded to said first substrate.
 3. The structure of claim 2, wherein theepitaxial layer is planarized prior to being bonded to said firstsubstrate.
 4. The structure of claim 2, wherein the epitaxial layer isplanarized by chemomechanical polishing.
 5. The structure of claim 2,wherein the epitaxial layer is planarized after the second substrate andgraded layer are removed.
 6. The structure of claim 2, wherein theepitaxial layer is planarized by chemomechanical polishing after thesecond substrate and graded layer are removed.
 7. The structure of claim1, wherein said first substrate comprises Si.
 8. The structure of claim7, wherein said first substrate includes a surface layer of SiO₂.
 9. Thestructure of claim 1, wherein the epitaxial layer comprisesSi_(1-x)Ge_(x) with 0.005<x<1.
 10. The structure of claim 9, wherein theepitaxial layer is planarized.
 11. The structure of claim 10, whereinthe epitaxial layer is planarized by chemomechanical polishing.
 12. Thestructure of claim 10, wherein said first substrate comprises Si. 13.The structure of claim 12, wherein said first substrate includes asurface layer of SiO₂.
 14. The structure of claim 1, wherein theepitaxial layer comprises Al_(y), (In_(x)Ga_(1-y)As.
 15. The structureof claim 1, wherein the epitaxial layer comprises In_(x)Ga_(1-x)As. 16.The structure of claim 1, wherein the epitaxial layer comprises GaAs.17. The structure of claim 14, wherein the epitaxial layer isplanarized.
 18. The structure of claim 17, wherein the epitaxial layeris planarized by chemomechanical polishing.
 19. The structure of claim17, wherein said first substrate comprises Si.
 20. The structure ofclaim 19, wherein said first substrate includes a surface layer of SiO₂.21. The structure of claim 1, wherein the epitaxial layer comprises(In_(x)Ga_(1-x))_(z)(As_(1-y)P_(y))_(1-z).
 22. The structure of claim 1,wherein the epitaxial layer comprises In_(x)Ga_(1-x)P.
 23. The structureof claim 1, wherein the epitaxial layer comprises InP.
 24. The structureof claim 21, wherein the epitaxial layer is planarized prior to beingbonded to said first substrate.
 25. The structure of claim 24, whereinthe epitaxial layer is planarized by chemomechanical polishing.
 26. Thestructure of claim 21, wherein said first substrate comprises Si. 27.The structure of claim 26, wherein said first substrate includes asurface layer of SiO₂.
 28. The structure of claim 2, wherein saidlayered structure comprises a crystalline substrate. said gradedcomposition layer and a threading dislocation density at the surface ofsaid second substrate which is less than 10⁷ cm⁻².
 29. The structure ofclaim 2, wherein said layered structure comprises a crystallinesubstrate. said graded composition layer, a uniform composition layerand a threading dislocation density at the surface of said secondsubstrate which is less than 10⁷ cm⁻²
 30. The structure of claim 29,wherein the surface of the layered structure is planarized.
 31. Thestructure of claim 30, wherein the surface of the layered structure isplanarized by chemomechanical polishing.
 32. The structure of claim 29,wherein said first substrate comprises Si.
 33. The structure of claim32, wherein said first substrate includes a surface layer of SiO₂. 34.The structure of claim 29, wherein the graded composition layercomprises Si_(1-x)Ge_(x) where the composition is approximately linearlyvaried from approximately x=0 to a final composition. and the uniformcomposition layer comprises Si_(1-y)Ge_(y).
 35. The structure of claim34, wherein the crystalline substrate comprises Si.
 36. The structure ofclaim in 35, wherein the epitaxial layer comprises Si_(1-x)Ge_(x) with0.005<x<1.
 37. The structure of claim 35, wherein y is approximately 1and the epitaxial layer comprises GaAs.
 38. The structure of claim 35,wherein y is approximately 1 and the epitaxial layer comprisesIn_(z)Ga_(1-z)P, where z is approximately 0.5.
 39. The structure ofclaim 34, wherein the epitaxial layer is planarized.
 40. The structureof claim 39, wherein the epitaxial layer is planarized bychemomechanical polishing.
 41. The structure of claim 39, wherein saidfirst substrate comprises Si.
 42. The structure of claim 41, whereinsaid first substrate includes a surface layer of SiO₂.
 43. The structureof claim 29, wherein the graded composition layer comprisesAl_(y)(ln_(x)Ga_(1-x))_(1-y)As, where the composition is approximatelylinearly varied from approximately x=0 to a the final composition, andthe uniform composition layer comprises Al_(w)(In_(z)Ga_(1-z))_(1-w)As.44. The structure of claim 43, wherein the crystalline substratecomprises a GaAs epitaxial layer on a Si substrate.
 45. The structure ofclaim 43, wherein the crystalline substrate comprises a Ge epitaxiallayer on a Si substrate.
 46. The structure of claim 43, wherein thecrystalline substrate comprises a Si_(1-x)Ge_(x) epitaxial layer on agraded composition Si_(1-y)Ge_(y) layer, which is on a Si substrate. 47.The structure of claim 43, wherein said epitaxial layer comprisesIn_(x)Ga_(1-x)As.
 48. The structure of claim 43, wherein said uniformcomposition layer comprises In_(x)Ga_(1-x)As, where x is approximately0.5, and said epitaxial layer comprises InP.
 49. The structure of claim43, wherein the epitaxial layer is planarized.
 50. The structure ofclaim 49, wherein the epitaxial layer is planarized by chemomechanicalpolishing.
 51. The structure of claim 49, wherein said first substratecomprises Si.
 52. The structure of claim 51, wherein said firstsubstrate includes a surface layer of SiO₂.
 53. The structure of claim29, wherein said graded composition layer comprises(In_(x)Ga_(1-x))_(z)(As_(1-y)P_(y))_(1-z), where the composition isapproximately linearly varied from approximately x=0 to a finalcomposition, and the uniform composition layer comprises(In_(u)Ga_(1-u))_(v)(As_(1-w)P_(w))_(1-v).
 54. The structure of claim53, wherein the crystalline substrate comprises a GaAs epitaxial layeron a Si substrate.
 55. The structure of claim 53, wherein thecrystalline substrate comprises a Si_(1-x)Ge_(x) epitaxial layer on agraded composition Si_(1-y)Ge_(y) layer, which is on a Si substrate. 56.The structure of claim 53, wherein the crystalline substrate comprises aGe epitaxial layer on a Si substrate.
 57. The structure of claim 53,wherein the surface of the layered structure is planarized.
 58. Thestructure of claim 57, wherein the surface of the layered structure isplanarized by chemomechanical polishing.
 59. The structure of claim 57,wherein said first substrate comprises Si.
 60. The structure of claim59, wherein said first substrate includes a surface layer of SiO₂. 61.The structure of claim 1, wherein said epitaxial layer comprisespatterned trenches or vias.
 62. A semiconductor structure comprising: afirst glass substrate; and an epitaxial layer bonded to said substrate,said epitaxial layer having a threading dislocation density of less than10⁷ cm⁻² and an in-plane lattice constant that is different from that ofa second substrate on which said epitaxial layer is fabricated.
 63. Thestructure of claim 62, wherein said epitaxial layer is a segment of apreviously fabricated layered structure including said second substratewith a composition graded layer and said epitaxial layer providedthereon, said second substrate and said graded layer being removedsubsequent to said layered structure being bonded to said glasssubstrate.
 64. The structure of claim 1, wherein said first glasssubstrate has a thermal expansion coefficient similar to that of saidsecond substrate.
 65. The structure of claim 62, wherein said epitaxiallayer comprises Si_(1-x)Ge_(x) with 0.005<x<1.
 66. The structure ofclaim 62, wherein said epitaxial layer comprisesAl_(y)(In_(x)Ga_(1-x))_(1-y)As.
 67. The structure of claim 62, whereinthe epitaxial layer comprises (In_(x)Ga_(1-x))_(z)(As_(1-y)P_(y))_(1-z).68. The structure of claim 62, wherein said epitaxial layer comprisespatterned trenches or vias.